Reactive Processors from Auckland University

Introduction: Reactive processors provide an alternative approach to the typical polling or interrupt mechanisms used by conventional processors for environment interaction. They were first developed at Auckland University, with the the first paper on it appearing in 2002. In the following, we present three generations of reactive processors that have been developed at Auckland University. The first generation consisted of simple processors that had no support for concurrency. The second generation of reactive architectures supported concurrency through the use of multiple processor cores. The current generation of reactive processors (called the third generation) provides multithreading support within a single core. While this work was being carried out here, research on reactive processors have also been on-going at Kiel University since 2004. Their research had proposed the first multithreaded design for reactive processors.

First generation reactive processors:

Reactive processors were proposed in 2002 [1] as a better-suited execution platform for reactive embedded systems compared to conventional processors. An embedded system typically interacts continuously with its adjoining environment through sensors and actuators. When implementing this interaction on conventional processors, inputs from the environmnet have traditionally been read through either polling or interrupt mechanisms. Polling is a simple procedure that checks for sensor values at regular intervals, irrespective of whether or not the sensor values have changed, resulting in a waste of CPU cycles, especially when sampling inputs that rarely change. Interrupts, on the other hand, combine preemption and priority in a single package, and are much more efficient compared to polling. The main drawbacks of interrupts, however, are:

1. unpredictability in the latency of an interrupt; and,
2. the associated code is very complex and difficult to debug.

Reactive processors were motivated by the need for alternative architectures that provided more predictable and structured models of interactions with the environment. The main idea to achieve this centred on an asynchronous hardware block, called the Abort Handling Block (AHB). The AHB works asynchronously with the main control unit of the processor to deal with preemption and priority resolution. Both preemption and priority resolution were achieved using instruction set architecture (ISA) extensions---we implemented a preemption instruction, called ABORT, that wraps a body of code. The body will execute until the preemption condition happens. Once this happens, program control jumps to a specified point (called the continuation address) outside the body. Priority is achieved through the simple nesting of ABORT instructions, with the outer abort conditions having higher priority. Using these extensions, we demonstrated that preemption and priority resolution can be achieved always within fixed bounded delay of at most one instruction cycle. The first set of reactive processors, called REFLIX [1, 2, 3] and REPIC [4], were extensions to conventional non-pipelined processors. However, these simple architectures demonstrated a very structured ISA driven approach to environment interaction that is both efficient and predictable. Subsequently, we proposed a fully pipelined version, called REMIC (short for REactive MICroprocessor) [8], that was a custom-built reactive microprocessor. REMIC had a three-stage pipeline, a reactive functional unit (RFU) for environment interaction through a set of signal ports, and a few reactive instructions in its ISA.

Second generation reactive processors:

The idea of reactive processors was actually inspired by the synchronous programming language Esterel. However, the first generation of reactive processors were designed for achieving better environment interaction rather than to support the execution of Esterel. The first reactive processor that could execute a two-threaded Esterel program was a multiprocessor using two REPIC cores [4]. We then developed a symmetric shared memory multiprocessor called EMPEROR [7] for executing up to 32 Esterel threads. This was subsequently extended to handle any number of Esterel threads using a compiler that dynamically resolved signals and executed many threads on a single processor [10].

We also developed an asymmetric shared memory multiprocessor called HiDRA [11] for supporting a set of concurrent, reactive tasks that communicate and synchronize using Esterel-like instructions. The corresponding concurrent assembly-level language called CRAL (concurrent reactive assembler language) was used for programming the ECL protocol stack example very efficiently.

Third generation reactive processors:

Researchers from Kiel University also proposed reactive processors to support the execution of Esterel. The first processor of this family called KEP1 (Kiel Esterel processor 1) was developed in 2004. Unlike the multiprocessor approach taken by researchers in Auckland, they developed a multithreading approach and corresponding compilation tools for supporting the full Esterel V5 language (KEP3a processor). More details on the KEP designs can be found at http://www.informatik.uni-kiel.de/rtsys/kep/. Our latest processor for the direct execution of Esterel, called STARPro [13], is also a multithreaded reactive processor. STARPro, unlike the KEP family, however, is pipelined and has a compiler that generates code using an intermediate format called unrolled concurrent control flow graph with surface and depth. This intermediate format closely resembles the original Esterel source. Some of the key differences between the approach taken by researchers at Auckland and Kiel to reactive processor design are listed here:

• Hardware usage: Second generation reactive processors from Auckland, being multiprocessor-based, were quite heavy on hardware usage. The KEP family improved on this by pursuing the multithreading approach to concurrency. However, their design is still quite hardware intensive compared to our current approach (STARPro) due to our greater use of software and the notion of “logical ticks.” Hence, our current processor, STARPro is very light on hardware resource usage.
• Scheduling: Esterel compilers typically use some kind of static scheduling for resolving signal statuses. The KEP compiler uses this approach together with an instruction to change the priority of threads during execution. Unlike this, our compiler for EMPEROR resolved signals dynamically using a dual-rail encoding of signals in the intermediate format. STARPro currently deals only with static scheduling with an instruction to change priority like KEP, but is currently being extended to deal with dynamic scheduling like EMPEROR.
• Pipelining: Reactive processors from Auckland have been pipelined since the REMIC processor.
• View of synchrony: Reactive processors from Auckland execute using the concept of logical ticks, where the PAUSE instruction is used to identify local tick boundaries, while the global tick is determined using barrier synchronization [7]. The KEP family of processors also have a notion of worst case execution time (WCET)-based ticks and hence are good for executing control-loops. They can also execute using logical ticks.

A paper summarising the primary contributions of the reactive processing approach and the primary differences with conventional processors appeared in [12].

Publications:

1. Z. Salcic, P. S. Roop, M. Biglari-Abhari, A. Bigdeli, “"REFLIX: A Processor Core for Reactive Embedded Applications", 12th International Conference on Filed Programmable Logic and Applications (FPL-02), Montpellier, France, 2002. [pdf]

2. P. S. Roop, Z. Salcic, M. Biglari-Abhari, A. Bigdeli, “A New Reactive Processor with Architecture Support for Control Dominated Embedded Systems”, IEEE International Conference on VLSI Design, IEEE CS Press, pp.189-194, 2003. [pdf]

3. Z. Salcic, P. S. Roop, M. Biglari-Abhari, A. Bigdeli, "REFLIX: A Processor Core with Native Support for Control Dominated Embedded Applications" Elsevier Journal of Microprocessors and Microsystems, 28, pp 13-25, 2004. [pdf]

4. P. S. Roop, E. Chow, J. Tong, M. W. S. Dayaratne, Z. Salcic, “RePIC- A New Processor Architecture Supporting Direct Esterel Execution”, School of Engineering Report No. 612, 2004. [pdf]

5. Z. Salcic, P. S. Roop, "Customizing Processor Cores to Support Reactivity", the 2004 International Conference on Engineering Reconfigurable Systems and Algorithms, Las Vegas, June 21-24, 2004.

6. Z. Salcic, P. S. Roop, D. Hui, I. Radojevic, "A New Architecture for Heterogeneous Embedded Systems", the 2004 International Conference on Embedded Systems and Applications, Las Vegas, June 21-24, 2004.

7. P. S. Roop, Z. Salcic, M. W. S. Dayaratne, "Towards Direct Execution of Esterel Programs on Reactive Processors", 4th ACM International Conference on Embedded Software (EMSOFT 04), Pisa, Italy, September 27-29, 2004. [pdf]

8. Z. Salcic, D. Hui, P. S. Roop and M. Biglari-Abhari, "REMIC - Design of a Reactive Embedded Microprocessor Core" Design Automation Conference, Proceedings of the 10th Asia and South Pacific Design Automation Conference (ASP-DAC 2005), China, 18-21 January, 2005, p.977-981. [pdf]

9. M.W. Sajeewa Dayaratne, P. S. Roop, Z. Salcic, "Direct Execution of Esterel Using Reactive Microprocessors", in proc. Synchronous Languages, Applications, and Programming, April 3rd, 2005, Edinburgh, Scotland. [pdf]

10. Li Hsien Yoong, Partha S Roop and Zoran Salcic, "Compiling Esterel for Distributed Execution", in proc. Synchronous Languages, Applications and Programming 2006, European Joint Conference on Theory and Practice of Software, March 25- April 2, Vienna, Austria, 2006. [pdf]

11. Z. Salcic, D. Hui, P. S. Roop and M. Biglari-Abhari, "HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems", Elsevier Journal of Microprocessors and Microsystems, 30, pp. 72-85, 2006. [pdf]

12. R. V. Hanxleden, X. Li, P. S. Roop, Z. Salcic, L. H. Yoong, “Reactive Processing for Reactive Systems”, European Research Consortium for Informatics and Mathematics News (ERCIM News), vol. 66, p28-29, 2006. [html]

13. S. Yuan, S. Andalam, L. H. Yoong, P. S. Roop and Z. Salcic, “STARPro – A New Multithreaded Direct Execution Platform for Esterel”, in proc. Model Driven high-Level Programming of Embedded Systems (SLA++P), European Joint Conference on Theory and Practice of Software, Budapest, Hungary, 2008. [pdf]

14. P. S. Roop, “Predictable Reactive Processors for Next Generation Computing: A Proposal”, School of Engineering Report Number 662, February 2008. [pdf]

Master of Engineering Thesis:

1. M. W. Sajeewa Dayaratne, “Direct Execution of Esterel using Reactive Microprocessors”, Master of Engineering (ME) thesis, University of Auckland, 2004
2. L. H. Yoong, “Compiling Esterel for Distributed execution”, Master of Engineering (ME) thesis, University of Auckland, 2005.
3. A. Wahid, “Architectural Support for Real-Time Scheduling on Embedded Microprocessors”, Master of Engineering (ME) thesis, University of Auckland, 2006.