Title |
Description |
Project Page |
Level |
People involved |
Status |
| Formal models of computation for heterogeneous embedded systems |
The project is searching for new models of computation that can naturally describe heterogeneous embedded systems and map onto heterogeneous multiple processor architecture that uses reactive processor as the basic building block. |
n/a
|
PhD |
Ivan Radojevic, Zoran Salcic, Partha Roop |
Current |
| Self Tuning Regulators |
The project deals with hardware implementation of self tuning regulators. One of the major problems is implementation of recursive least squares algorithm with guaranteed stability. |
n/a
|
PhD |
Zoran Salcic, Sing Kiong Nguang, Jiaying Cao |
Current |
| HiDRA - HybriD Reactive Architecture for Heterogeneous Embedded Systems |
The project explores the architectures that support heterogeneous embedded systems applications. The basic building block is customisable reactive processor core. The architecture enables implementation of application processes in software and/or hardware. Simple, efficient dual-port memory mechanism is used for communication between processor cores and hardware functional units. |
n/a
|
PhD |
Zoran Salcic, Morteza Biglari-Abhari, Partha Roop, Sergelen Bazarragchaa, Dong Hui |
Current |
| RePIC |
Adding reactivity features to standard PIC processor. The new processor, called RePIC is described in VHDL and implemented on an FPGA device. |
Link
|
4th Year |
Edmund Chow, Joice Tong, partha Roop, Zoran Salcic |
Completed |
