Department of Electrical and Computer Engineering

Parallel and reconfigurable computing

Parallel computing is more important than ever, given the mainstream move towards multi-core processors. In this group we investigate various aspects of parallel and reconfigurable computing. This ranges from fundamental problems, like task scheduling, to the development of visual tools.

A strong focus is on the exploitation of new forms of parallelism, be it the use of reconfigurable hardware for high performance computing or the parallelisation of (object oriented) desktop applications.

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Even though this research area has existed for many decades, parallel computing is still challenging with many unsolved problems. The physical limits of processor technology and the resulting shift towards multi-core systems makes this area more relevant and important than ever. Our research includes, but is not limited to, the following topics:

Desktop parallelisation

Modern computer systems have more than one processor-core. To benefit from this processing power, we need to parallelise our programs. For desktop applications, like browsers, word processing etc, this mainly means that object oriented (OO) applications have to be parallelised. We investigate novel methods and techniques for the parallelisation of such programs without jeopardising the benefits of high-level OO languages.


Crucial for the efficiency of a parallel program is how the (sub)tasks of the program are mapped and ordered on the processors of the system. In task scheduling, the program is represented by a graph, where the nodes represent the tasks and the edges the communication between the tasks. The objective is then to find the best scheduling of this graph on the processors that allows the fastest execution of the program. Unfortunately, this is a very difficult optimisation problem (NP-hard). We investigate realistic system models, novel approaches and algorithms for this problem to make scheduling more efficient and accurate.

Reconfigurable computing

A reconfigurable hardware system constructed from FPGAs can provide much higher performance for certain applications than general purpose parallel systems. The advantage comes from the potentially much higher concurrency of many small processing elements that can work in parallel. Unfortunately, configuring a reconfigurable system is even more challenging than programming a parallel system. We investigate how reconfigurable hardware can be integrated into general purpose parallel computing. We develop tools based on high level programming languages and investigate how reconfigurable systems can be used in certain areas, eg. bioengineering.

Visualisation and development tools

For fast and efficient development of programs, development tools are indispensable. Strangely though, there are not many powerful tools available for parallel programming, even though it is more involved and complex than sequential programming. We investigate such tools, with a focus on visual aids. For example, we develop tools that can visualise the dependences between code parts or display the scheduling of the tasks on processors. The design aim includes a deep integration with the existing development process.

To undertake this research, the Parallel and Reconfigurable Computing Lab in the department possesses several parallel and reconfigurable computing systems.

Square Kilometre Array (SKA)

The Square Kilometre Array (SKA) will soon be the world's largest radio telescope array and is currently in its (pre-)construction phase. With 11 member countries involved at its current stage, it is a mega-science project with a projected budget of more than half a billion Euros. Upon its completion, it will help radio astronomers and scientists to investigate the major open questions in science such as strong field physics, probing the Cosmic Dawn, and the Cradle of Life.

Large antenna arrays will be built on selected sites in South Africa and Australia, though one of the SKA’s biggest challenges would remain its unprecedented processing and data communication requirements. Gigantic streams of data signals will need to be processed in real time, with a rate that will exceed the culmination of global internet traffic in recent years, thus posing major engineering challenges.

The SKA’s construction and design is largely a High Performance Computing and Data Science project that is reflective of the challenges we will see in future supercomputers and big data projects. We are currently investigating and designing high performance solutions for radio astronomical algorithms and methods – mostly based on FPGAs – programmed with high level approaches.


Dr Oliver Sinnen
Senior Lecturer
Phone: +64 9 373 7599 ext 88285